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Espressif Systems /ESP32-S3 /SENSITIVE /CORE_1_DRAM0_PMS_MONITOR_1

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Interpret as CORE_1_DRAM0_PMS_MONITOR_1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR)CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR 0 (CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN)CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN

Description

core1 dram0 permission monitor configuration register 1

Fields

CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR

Set 1 to clear core1 dram0 permission monior interrupt.
CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN

Set 1 to enable core1 dram0 permission monitor interrupt.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data